Electronic systems and circuits have made a significant contribution towards the advancement of modem society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems facilitate increased productivity and cost reduction in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Frequently, electronic systems designed to provide these results comprise a variety of components including application specific integrate circuits (ASIC) arranged on printed circuit boards. Efficient testing of ASIC chips and printed circuit boards is an important part of assuring electrical connections between ASICs and printed circuit boards do not result in inappropriate electrical shorts or open circuit conditions.
Historically, in-circuit tests were relied on to test electrical circuits. Traditional in-circuit testing techniques include test operation dedicated pogo pins that contact testing pads on the bottom side of a printed circuit board. A tester utilizes the pogo pins to probe the testing pads by activating certain portions of the printed circuit board and observing the results. Pogo pin techniques are relatively expensive and unreliable. For example, pogo pin pads usually take up valuable circuit board resources and it is often difficult to get pads to accurately line up with pogo pins in the tester. Complex ASICs and circuit boards typically require numerous pogo pins and testing pads, resulting in testing pad density problems such as difficulty in finding room for enough probe points.
As the complexity of ASICs advance, designers rely more on built in self test (BIST) diagnostics capability for effective circuit testing. Modem BIST techniques typically include the insertion of a scan test system in an ASIC. Typically, scan test systems rely on the application of test vectors to initiate scan test operations and to stimulate certain aspects of the ASIC or printed circuit board. A scan test system usually includes a scan test enable signal that is part of a scan test initiation operation. Some scan test systems rely on communication of a special test vector to activate the scan test enable signal and other systems rely on a dedicated scan test enable pin to provide a dedicated scan test enable signal. While BIST techniques usually require less resources than pogo pin in-circuit testing, generating special test vectors and/or providing dedicated scan test pins for scan testing operations expends valuable resources.
Creating sequences of signals to utilize as test vectors that a device (e.g., an ASIC) decodes to activate a scan test enable signal is problematic. Usually, a scan test enable signal is utilized to put the ASIC or circuit board in scan test mode and it is detrimental to the functionality of a chip to go into test mode during normal operations. Typically, a test vector utilized to initiate scan test enable signal is required to be a very unique sequence of signals to avoid the test vector occurring during normal operations in a system and accidentally activating scan test mode. Thus, significant resources are often expended determining an otherwise “illegal” sequence of signals that has an extremely low probability of occurring. Additional resources are expended designing an algorithm that recognizes when the special sequence of illegal signals does occur and interpreting the special illegal sequence as a command to activate a scan test enable signal. Optimal results are achieved if the “illegal” sequence of signals only happens when entering a test mode is desired. However, even after expending significant resources designers can not typically guarantee the special “illegal” sequence will not occur accidentally and put an ASIC in test mode at an inappropriate time.
Some BIST techniques attempt to avoid the difficulties of special sequence test vectors by including a pin dedicated to the communication of a scan test enable signal. However, this approach also uses up valuable resources. Usually, there is a limited number of pins on an ASIC or printed circuit board and tying up one or more of those pins for dedicated communication of a scan test enable signal results in fewer pins being available for other testing functions and normal functional operations.
What is required is a system and method that activates a scan test enable signal without the requirement of complex special signal sequences transmitted via a pin dedicated solely to scan test enable signal communication. The system and method should permit a designer to efficiently and effectively assert a scan test enable signal. The electronic system and method should minimize adverse redesign impacts to existing ASIC and circuit board designs and facilitate utilization of existing scan test architectures.